OP Stack
MIPS.sol

Fault proof VM: MIPS.sol

The MIPS.sol smart contract implements an onchain MIPS III virtual machine as part of Optimism's Fault Proof system. This implementation works together with an off-chain Go implementation to form Cannon, which enables onchain verification of disputed L2 state transitions.

Architecture and implementation

The contract is designed to work alongside its offchain Go implementation as a stateless system where all execution state is passed in as parameters. This allows multiple dispute games to share a single deployment while maintaining consistent behavior across environments:

  • Component architecture
    • Offchain component executes MIPS instructions across multiple threads for disputed L2 state transitions
    • Onchain component (MIPS.sol) executes single instructions with provided state and memory proofs
    • Both maintain deterministic execution through careful thread state management
  • Key implementation features
    • Single immutable variable - the PreimageOracle contract address for L1/L2 state data access
    • VM state passed as tightly packed struct containing registers, program counter, and thread states
    • Memory implemented as binary Merkle tree with 27-level depth and 32-byte leaf values
    • Support for 8-byte reads/writes in 64-bit mode
    • Big-Endian byte ordering aligned with EVM's native ordering
    • Minimal syscalls focused on PreimageOracle interactions and thread management

Memory and state management

The memory and state management system in MIPS.sol implements a sophisticated architecture optimized for 64-bit addressing and multithreaded operations:

  • Memory architecture
    • Binary Merkle tree with fixed depth of 28 levels for full 64-bit address space support
    • 32-byte leaf values enable efficient memory operations
    • Thread-safe memory access with deterministic scheduling
    • Supports up to 8-byte atomic operations in 64-bit mode
  • State management
    • Stateless contract design with execution state passed as parameters
    • Enhanced 64-bit memory addressing supporting theoretical 16 exabytes of virtual memory
    • Thread states include register contexts, program counter, and memory management data
    • Maintains consistent thread states between onchain and offchain implementations

Thread management and PreimageOracle integration

The implementation features sophisticated thread management integrated with PreimageOracle interactions:

  • Thread control and scheduling
    • Deterministic multi-threading using fixed sequence traversal
    • Context switching with sleep, yield, and wait operations
    • Wake signals for thread activation based on memory conditions
    • Forced thread preemption to prevent starvation
  • PreimageOracle integration
    • Specialized syscalls for PreimageOracle communication
    • Support for concurrent PreimageOracle interactions
    • Thread-safe state access and verification
    • Up to 8-byte reads for improved efficiency

Key Functions

The main external interface is the step function which executes a single MIPS instruction:

  • Takes packed VM state and memory proofs as input
  • Executes one instruction according to MIPS III spec
  • Returns a state hash incorporating execution status
  • Handles memory access via Merkle proofs
  • Manages PreimageOracle interactions for system calls

Internal functions handle specific instruction types:

  • handleBranch - Implements branch instructions
  • handleJump - Handles jump operations
  • handleHiLo - Manages HI/LO register operations
  • handleSyscall - Processes system calls

The implementation prioritizes gas efficiency while maintaining the minimal functionality needed for fault proof verification.

Table of supported MIPS instructions

Instruction NameOpcode Num.Funct Num.Other Num.
SYSCALL (System Call)0x000x0C-
J (Jump)0x02--
JR (Jump Register)0x000x08-
JAL (Jump and Link)0x03--
JALR (Jump and Link Register)0x000x09-
BEQ (Branch on Equal)0x04--
BNE (Branch on Not Equal)0x05--
BLEZ (Branch on Less Than or Equal to Zero)0x06--
BGTZ (Branch on Greater Than Zero)0x07--
BLTZ (Branch on Less Than Zero)0x01-0x00
BGEZ (Branch on Greater Than or Equal to Zero)0x01-0x01
MOVZ (Move Conditional on Zero)0x000x0A-
MOVN (Move Conditional on Not Zero)0x000x0B-
MFHI (Move from HI)0x000x10-
MTHI (Move to HI)0x000x11-
MFLO (Move from LO)0x000x12-
MTLO (Move to LO)0x000x13-
MULT (Multiply Word)0x000x18-
MULTU (Multiply Unsigned Word)0x000x19-
DIV (Divide Word)0x000x1A-
DIVU (Divide Unsigned Word)0x000x1B-
ADD (Add Word)0x000x20-
ADDU (Add Unsigned Word)0x000x21-
ADDI (Add Immediate Word)0x08--
ADDIU (Add Immediate Unsigned Word)0x09--
SUB (Subtract Word)0x000x22-
SUBU (Subtract Unsigned Word)0x000x23-
SLT (Set on Less Than)0x000x2A-
SLTU (Set on Less Than Unsigned)0x000x2B-
SLTI (Set on Less Than Immediate)0x0A--
SLTIU (Set on Less Than Immediate Unsigned)0x0B--
AND (And)0x000x24-
ANDI (And Immediate)0x0C--
OR (Or)0x000x25-
ORI (Or Immediate)0x0D--
XOR (Exclusive Or)0x000x26-
XORI (Exclusive Or Immediate)0x0E--
NOR (Nor)0x000x27-
SLL (Shift Word Left Logical)0x000x00-
SRL (Shift Word Right Logical)0x000x02-
SRA (Shift Word Right Arithmetic)0x000x03-
SLLV (Shift Word Left Logical Variable)0x000x04-
SRLV (Shift Word Right Logical Variable)0x000x06-
SRAV (Shift Word Right Arithmetic Variable)0x000x07-
MUL (Multiply Word to Register)0x1C0x02-
CLZ (Count Leading Zeros in Word)0x1C0x20-
CLO (Count Leading Ones in Word)0x1C0x21-
LUI (Load Upper Immediate)0x0F--
LL (Load Linked Word)0x30--
LB (Load Byte)0x20--
LBU (Load Byte Unsigned)0x24--
LH (Load Halfword)0x21--
LHU (Load Halfword Unsigned)0x25--
LW (Load Word)0x23--
LWL (Load Word Left)0x22--
LWR (Load Word Right)0x26--
SB (Store Byte)0x28--
SH (Store Halfword)0x29--
SW (Store Word)0x2B--
SWL (Store Word Left)0x2A--
SWR (Store Word Right)0x2E--
SC (Store Conditional Word)0x38--
SYNC (Synchronize Shared Memory)0x000x0F-

Further reading